• Level Max number of gates; NOT gate는 세지 않는다.

  • NAND ↔ NOR

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  • Circuit Design

    • SOP → NAND only → NOR only + NOT

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      • Insert 2 circles in odd levels to make NAND only

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    • POS → NOR only → NAND only + NOT

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      • Insert 2 circles in even Levels to make NOR only

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  • Gate Delay

    • Hazard

      • Glitch: unwanted pulse → error
      • Hazard: potential for glitches
        • static-1 hazard: 1이다가 0으로 튐; SOP에서 발생
        • static-0 hazard: 0이다가 1으로 튐; POS에서 발생

    • Eliminate Hazard: add Redundant PIs : add PIs which are not considered due to consensus thm

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